Low Power Reversible Parallel Binary Adder/Subtractor

摘要

In recent years, Reversible Logic is becoming more and more prominenttechnology having its applications in Low Power CMOS, Quantum Computing,Nanotechnology, and Optical Computing. Reversibility plays an important rolewhen energy efficient computations are considered. In this paper, Reversibleeight-bit Parallel Binary Adder/Subtractor with Design I, Design II and DesignIII are proposed. In all the three design approaches, the full Adder andSubtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using numberreversible gates, Garbage input/outputs and Quantum Cost. It is observed thatReversible eight-bit Parallel Binary Adder/Subtractor with Design III isefficient compared to Design I, Design II and existing design.